This invention relates generally to the field of electronic devices and more particularly to a method for forming an embedded FLASH memory circuit with reduced processing steps.
Electronic equipment such as televisions, telephones, radios, and computers are often constructed using semiconductor components, such as integrated circuits, memory chips, and the like. The semiconductor components are typically constructed from various microelectronic devices fabricated on a semiconductor substrate, such as transistors, capacitors, diodes, resistors, and the like. Each microelectronic device is typically a pattern of conductor, semiconductor, and insulator regions formed on the semiconductor substrate.
FLASH memory, also known as FLASH EPROM or FLASH EEPROM, is a semiconductor component that is formed from an array of memory cells with each cell having a floating gate transistor. Data can be written to each cell within the array, but the data is erased in blocks of cells. Each cell is a floating gate transistor having a source, drain, floating gate, and a control gate. The floating gate uses channel hot electrons for writing from the drain and uses Fowler-Nordheim tunneling for erasure from the source. The sources of each floating gate in each cell in a row of the array are connected to form a source line.
Embedding FLASH memory circuits in CMOS logic circuits (embedded FLASH) is finding increasing usage in building more complex integrated circuits such as digital signal processors for applications such as hard disk controllers.
Traditionally, in CMOS integrated circuit fabrication, the polycrystalline silicon gates of both the NMOS and PMOS transistors were doped n-type with phosphorous through diffusion or ion implantation with no additional photolithography masks. The shrinking dimensions of the transistors in current use in CMOS integrated circuits have led to the gate of the NMOS transistors being doped n-type with this dopant being blocked from entering the gates of the PMOS transistors using a photolithographic pattern and masking step. The gates of the PMOS transistors are implanted p-type during the formation of the source and drain regions of the PMOS transistors. This process results in the proper threshold voltage in both the NMOS and PMOS transistors. For embedded FLASH circuits these doping requirements for the CMOS gates results in two critical masking levels to separately define the CMOS gates and the FLASH memory gate adding high processing cost and increased processing complexity. In addition, the problems associated with etching doped and undoped polycrystalline silicon to form the CMOS gates sometimes requires the use of an additional masking step (it is known in the art that doped polycrystalline silicon films etches at a faster rate than undoped polycrystalline silicon films). There is therefore a need for a method to simultaneously form the FLASH memory gate stack and the CMOS gates that reduces the number of masking levels reducing cost and process complexity.
Accordingly, a need has arisen for a simplified process to form embedded FLASH integrated circuits. The present invention provides method that accomplishes this through a reduction in number of masking levels and improved etching processes. One method of the instant invention comprises: forming a first photoresist film over a semiconductor substrate; patterning said first photoresist film to expose a first region of a polycrystalline film where a control gate will be formed in a FLASH memory cell and masking a second region of said polycrystalline film wherein said second region of said polycrystalline silicon film region will be used to form a gate structure of a NMOS transistor and a gate structure of a PMOS transistor; and partially etching said first region of said polycrystalline film. The embodiment further comprises: removing said first photoresist film; forming and patterning a second photoresist film; and etching said polycrystalline film to simultaneously form a FLASH memory cell gate stack structure, said gate structure of said NMOS transistor and said gate structure of said PMOS transistor.